1. Field of the Invention
The present invention generally relates to technology about semiconductor device, and particularly to the technology about static random access memory (SRAM).
2. Description of Related Art
The invention is directed to the semiconductor structure of SRAM device, which is a memory cell based on the structure of 6 transistor (6T). The memory cell includes two P-type meta-oxide-semiconductor (MOS), PMOS, transistors and four N-type meta-oxide-semiconductor, NMOS, transistors. These MOS transistor can be directly formed on a silicon substrate. In a further technology development, it can be fabricated by use of silicon on insulator (SOI) substrate. In semiconductor fabrication, multiple P-well lines and multiple N-well lines in a long line shape and are formed by interleaving in the substrate. The two PMOS transistor are formed over the N-well line. The four PMOS transistors are grouped into two groups, respectively formed over P-well lines located at both sides of the N-well line.
To the SOI substrate, the well lines are formed in the top silicon. A substrate voltage is applied to the whole well line from an end terminal. The transistors at the far end would rather possibly accumulate the charges, which cause decrease of the threshold voltage (Vt). As a result, it causes the issues such as instability or leakage current.
Therefore, the design for the 6T SRAM structure is still under development, so to improve the performance of the SRAM.